1. Field of the Invention
The current invention relates to input/output buffer information specification (IBIS) model generation, and more particularly, to IBIS model generation for multi-chip modules (MCMs) and similar devices.
2. Description of the Related Art
Integrated circuit (IC) devices are electronic devices containing one or more semiconductor dies, or “chips.” Chips have been successfully designed for decades using software known as electronic design automation (EDA) tools. To design an IC, a first “cut” of the design is done and then it is simulated to see how well the design works. The results are used by designer to correct any shortcomings in the design and the cycle is repeated until the desired results are obtained. The simulator uses a software model of the design, and different operating parameters are applied to the model, such as different clock speeds, signal inputs, temperature ranges, operating voltages, etc., to determine how well the design operates in a given application. One well-known model is referred to as a SPICE (Simulation Program with Integrated Circuits Emphasis) model, which relies on detailed design and component information. A SPICE model can allow accurate but slow simulation of the chip. However, the information needed for the model is considered proprietary by the manufacturer of the chip and may not be shared freely with customers.
To simplify system designs and to satisfy the desire for more functionality in smaller packages, a new kind of device, known as a multi-chip module (MCM) has been developed. An MCM has multiple chips mounted on a substrate, such as a printed circuit board (PCB), and encapsulated together to form a single packaged device. One example of an MCM is a system-in-a-package (SiP) device, wherein one module performs many or even all of the electronic functions of an electronic system. The chips in an MCM may be connected to each other as well as to external pins of the MCM package. In some cases, one or more package-external pins are connected to multiple input/output (I/O) buffers located on multiple chips. And as the clock speed of chips increases, the behavior of interface circuitry (e.g., I/O buffers) on the chips and the wiring between the chips become critical for proper operation.
Timing, transmission-line effects, and power considerations must be considered by system designers to get a reliable system. The modeling, analysis and correction of these effects is generally known as signal integrity (SI) analysis. To determine if the chips are correctly interfaced, a signal integrity (SI) analyst models the interconnected chips. Because of the complexity of the SPICE models for the individual chips, simulating the interconnected chips can be impractically slow and unwieldy, assuming that the individual SPICE models are made available by the manufacturer.
Alternatively, modeling multiple chips interconnected together allows a chip designer to modify the interface circuitry on one or more of the chips prior to final design so that the chips work better together. In this example, the bottleneck in the design cycle is the same for the chip designer as it is for the system designer: having the proper models to simulate the interconnected chips and that the simulation be fast enough to be practical.
An alternative to the detailed and propriety component-level SPICE model is a behavioral model of a device. A behavioral model treats the device as a black box and describes how its buffers and/or pins interact with the outside world without disclosing the device's detailed design and component information. For example, a behavioral model can provide current vs. voltage (I/V) information for different operational modes of the pins of a device. A behavioral model generally allows for faster simulation of device interaction than does a SPICE model of the equivalent device.
A widely-used behavioral simulation standard for IC devices is defined by the input/output (I/O) buffer information specification (IBIS), also known as ANSI/EIA-656, and is incorporated herein by reference in its entirety. IBIS has been evolving since version 1.0 was introduced in 1993. An example of an IBIS modeling tool, or modeler, can be found in the Hyperlynx suite of EDA tools from Mentor Graphics Corp., of Wilsonville, Oreg. IBIS model files are formatted as human-readable ASCII text files which can be parsed by appropriate software. The information in IBIS model files includes I/V characteristics for each pin, rise and fall time characteristics for each pin, and information about the package of the device. The I/V characteristics reflect many non-linear aspects of an I/O buffer design, such as diodes for electro-static discharge (ESD) protection, and pull-up and pull-down transistor characteristics. The information in an IBIS model file may be: (i) derived from a SPICE, or similar, model, by conversion or simulation of the model, (ii) obtained empirically by measurement, or (iii) obtained by a combination of both.
An IBIS model file uses keywords in brackets, such as [Component], [Package], [Pin], and [Model], followed by textual information describing the keyword item. For example, the [Component] keyword is followed by the name of the device (i.e., an identifier for the IC) that is modeled in the file, while the [Package] keyword is followed by default values for the resistance, inductance, and capacitance of the bond wire and pin combination of the device package, wherein the values are represented by the R_pkg, L_pkg, and C_pkg parameters, respectively. Where appropriate and available, three values are provided for parameters and/or sub-parameters: typical, minimum, and maximum values. In accordance with the present standard, if values are not available, then the reserved word “NA” is used.
The [Pin] keyword is followed by a listing of all the pins of the device, including, for each pin, the name of the associated signal path, the name of the associated I/V model, and pin-specific package-related resistance, inductance, and capacitance information, which are represented by the R_pin, L_pin, and C_pin parameters, respectively.
The [Model] keyword is followed by information for a particular I/V model, including: (i) the output capacitance, represented by the C_comp parameter, (ii) I/V data for pull-down, pull-up, ground-clamp diode, and power-clamp diode, which appears following the [Pulldown], [Pullup], [GND_clamp], and [POWER_clamp] keywords, respectively, to the extent the blocks are present in the device, and (iii) the ramp time for rising and falling transitions of the pull-up and pull-down structures, which are represented under the [Ramp] keyword by the dV/dt_r and dV/dt_f parameters, respectively. If more detailed information is desired for transitions between logic states represented by the pull-up and pull-down structures, voltage versus time (V/T) data can be provided for the rising and falling waveforms, under the [Rising Waveform] and [Falling Waveform] keywords, respectively. Multiple rising and falling waveform tables may be provided to account for multiple load types.
If a buffer does not include clamp-diodes, the corresponding keywords (i.e., [GND_clamp] and [Power_clamp]) and their respective data may be omitted from the corresponding model. The clamp-diode characteristics are meant to be modeled in parallel with the output transistor characteristics so that the clamp-diode characteristics are present even when the output buffer is off (i.e., in a high-impedance state). The I/V data includes a range of voltage values, and for each voltage value, values for the typical, minimum, and maximum corresponding current. In accordance with the IBIS standard, voltages in the pull-up and power-clamp sections are relative to Vcc, a power supply voltage, i.e., the voltage shown is equal to Vcc minus the output voltage, which may measured or derived. A particular I/V model in an IBIS model file may apply to any number of the pins of the modeled device.
FIG. 1 shows a schematic representation 100 of the basic elements of an IBIS model for an exemplary CMOS I/O buffer. It should be noted that the invention is not limited to CMOS technology and applies to other semiconductor technologies, such as bipolar technology. Within an IBIS model file, the model for a particular pin may be referenced by the [Pin] keyword and defined under the [Model] keyword. The basic elements of an IBIS model are represented by the numbered blocks in FIG. 1. Block 1 contains pull-down output transistor 101, modeled in an IBIS model file by the I/V data under the [Pulldown] keyword, describing characteristics of the buffer when driven low. Block 2 contains pull-up output transistor 102, modeled by the I/V data under the [Pullup] keyword, describing characteristics of the buffer when driven high. Block 3 contains ESD-protection diodes 103 and 104, modeled by the I/V data under the [GND_clamp] and [Power_clamp] keywords, respectively. Block 4 refers to the transition time of the output as it switches from one logic state to another, modeled under the [Ramp] keyword. Block 4 may be used for modeling the AC behavior of the pin. Block 5 represents parasitics (resistance, inductance, and/or capacitance) of the semiconductor die and the package, modeled under the [Package], [Pin], and/or [Model] keywords.
I/O (i.e., bi-directional) and output-only buffers models include all five blocks of FIG. 1. Input-only buffer models, however, may only need blocks 3 and 5 as they do not contain any output transistors. Thus, IBIS models for pins that serve input-only buffers typically do not include I/V information for pull-up elements, pull-down elements, and ramp time, and do not include the associated keywords (i.e., [Pullup], [Pulldown], and [Ramp]).
FIG. 2 shows a simplified diagram of MCM 200 containing four semiconductor dies, specifically, chips 201, 202, 203, and 204, each having a buffer connected to package-external pin 205, namely, buffers 206, 207, 208, and 209, respectively. Since previously-extant behavioral-modeling standards, such as IBIS, do not provide a satisfactory methodology for modeling and simulating system designs such MCMs, a new approach to modeling multiple-chip embodiments is needed.